53% Space Savings vs. Monolithic Solution Reduced System Inductance and Capacitance 3.3V Operating Supply Voltage Fully Synchronous to Positive Clock Edge Clock Frequenci.
The package and design provides performance enhancements via a 50% reduction in capacitance vs. four monolithic devices.
The WED3DL644V is a 4Mx64 Synchronous DRAM configured as 4x1Mx64. The SDRAM BGA is constructed with four 4Mx16 SDRAM die mounted on a multi-layer laminate substrate and packaged in a 153 lead, 17mm by 23mm, BGA. The WED3DL644V is available in clock sp.
Image gallery
TAGS
Manufacturer
Related datasheet
